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dsPIC30F6011/6012/6013/6014

DS70117F-page 106

2006 Microchip Technology Inc.

16.3.4

TRANSMIT INTERRUPT

The transmit interrupt flag (U1TXIF or U2TXIF) is

located in the corresponding interrupt flag register.

The transmitter generates an edge to set the UxTXIF

bit. The condition for generating the interrupt depends

on the UTXISEL control bit:

If UTXISEL = 0, an interrupt is generated when

a word is transferred from the transmit buffer to

the Transmit Shift register (UxTSR). This implies

that the transmit buffer has at least one empty

word.

If UTXISEL = 1, an interrupt is generated when

a word is transferred from the transmit buffer to

the Transmit Shift register (UxTSR) and the

transmit buffer is empty.

Switching between the two Interrupt modes during

operation is possible and sometimes offers more

flexibility.

16.3.5

TRANSMIT BREAK

Setting the UTXBRK bit (UxSTA<11>) will cause the

UxTX line to be driven to logic ‘0’. The UTXBRK bit

overrides all transmission activity. Therefore, the user

should generally wait for the transmitter to be Idle

before setting UTXBRK.

To send a break character, the UTXBRK bit must be set

by software and must remain set for a minimum of 13

baud clock cycles. The UTXBRK bit is then cleared by

software to generate Stop bits. The user must wait for

a duration of at least one or two baud clock cycles in

order to ensure a valid Stop bit(s) before reloading the

UxTXB, or starting other transmitter activity. Transmis-

sion of a break character does not generate a

transmit interrupt.

16.4

Receiving Data

16.4.1

RECEIVING IN 8-BIT OR 9-BIT

DATA MODE

The following steps must be performed while receiving

8-bit or 9-bit data:

Set up the UART (see Section 16.3.1 “Trans-

mitting in 8-bit data mode”).

Enable the UART (see Section 16.3.1 “Trans-

mitting in 8-bit data mode”).

A receive interrupt will be generated when one

or more data words have been received,

depending on the receive interrupt settings

specified by the URXISEL bits (UxSTA<7:6>).

Read the OERR bit to determine if an overrun

error has occurred. The OERR bit must be reset

in software.

Read the received data from UxRXREG. The act

of reading UxRXREG will move the next word to

the top of the receive FIFO, and the PERR and

FERR values will be updated.

16.4.2

RECEIVE BUFFER (UXRXB)

The receive buffer is 4 words deep. Including the

Receive Shift register (UxRSR), the user effectively

has a 5-word deep FIFO buffer.

URXDA (UxSTA<0>) = 1 indicates that the receive

buffer has data available. URXDA = 0 implies that the

buffer is empty. If a user attempts to read an empty

buffer, the old values in the buffer will be read and no

data shift will occur within the FIFO.

The FIFO is reset during any device Reset. It is not

affected when the device enters or wakes up from a

power-saving mode.

16.4.3

RECEIVE INTERRUPT

The receive interrupt flag (U1RXIF or U2RXIF) can be

read from the corresponding interrupt flag register. The

interrupt flag is set by an edge generated by the

receiver. The condition for setting the receive interrupt

flag depends on the settings specified by the

URXISEL<1:0> (UxSTA<7:6>) control bits.

If URXISEL<1:0> = 00 or 01, an interrupt is gen-

erated every time a data word is transferred

from the Receive Shift register (UxRSR) to the

receive buffer. There may be one or more

characters in the receive buffer.

If URXISEL<1:0> = 10, an interrupt is generated

when a word is transferred from the Receive Shift

result of the transfer, contains 3 characters.

If URXISEL<1:0> = 11, an interrupt is set when

a word is transferred from the Receive Shift reg-

ister (UxRSR) to the receive buffer, which as a

result of the transfer, contains 4 characters (i.e.,

becomes full).

Switching between the Interrupt modes during opera-

tion is possible, though generally not advisable during

normal operation.

16.5

Reception Error Handling

16.5.1

RECEIVE BUFFER OVERRUN

ERROR (OERR BIT)

The OERR bit (UxSTA<1>) is set if all of the following

conditions occur:

The receive buffer is full.

The Receive Shift register is full, but unable to

transfer the character to the receive buffer.

The Stop bit of the character in the UxRSR is

detected, indicating that the UxRSR needs to

transfer the character to the buffer.

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